1. Field of the Invention
The present invention relates to a scan test system for a semiconductor device, for inspecting the short/open of a wiring connected between semiconductor devices.
2. Description of the Prior Art
FIG. 5 is a schematic constitution diagram of a conventional scan test system for a semiconductor device shown, for instance, in JP-A-05/322989 (1993). The semiconductor device of the system comprises a JTAG boundary scan register that can inspect the short/open of a wiring between the devices digital-connected. FIG. 5 shows a semiconductor device 2, a digital input/output pin 6, an internal system logic 8, a JTAG specification boundary scan register or JTAG boundary scan register 9, a boundary scan register chain 10, TDO (Test Data Output) 11, TMS (Test Mode Select) 12, TDI (Test Data Input) 13, TCK (Test Clock) 14, and a TAPC (Test Access Port Controller) 15.
FIG. 6 illustrates a basic constitution of the boundary scan register 9. FIG. 6 shows an input multiplexer 16, a shift register stage 17, a parallel output stage 18, data input 19, Shift-DR (shift data register signal) 20, Clock-DR (clock data register signal) 21, Update-DR (update data register signal) 22, and data output 23.
The operation of the conventional scan test system for a semiconductor device will next be described.
The built-in boundary scan register 9 of each digital input/output pin 6 performs the basic operations of capture (Capture), shift (Shift), and update (Update) depending on the state transition of the TAPC 15. This state transition of the TAPC 15 is done by an input to TMS, and the TAPC 15 gives a control signal necessary for the operation in each state.
These basic operations will next be described.
(1) Capture Operation
A value from a system circuit, that is, an internal system logic and an external system logic (herein, corresponding to the input from an analog sensor) is captured into the shift register stage 17 of the boundary scan register 9.
(2) Shift Operation
The scan operation of a test data register is done. When the boundary scan register 9 is being specified by the present instruction, this test data register is connected between TDI 13 and TDO 11, and a shift to the serial output direction is thereby caused by one bit synchronizing with TCK 14.
(3) Update Operation
the parallel output stage 18 of the test data register is updated. When boundary scan register 9 is being specified by the present instruction, the data is transmitted from the shift register stage 17 of the boundary scan register 9 to the parallel output stage 18 synchronizing with TCK14. By the way, it is when Shift-DR 20 or Capture-DR becomes active that Clock-DR 21 becomes active.
The conventional scan test system for a semiconductor device is constituted as mentioned above. Therefore, because the conventional JTAG boundary scan register 9 is configured with a digital terminal, although it can detect the short/open of an wiring connected between digital-connected devices, it needs monitoring the wiring by additionally contacting the probes thereon in order to detect the short/open of an analog-connected wiring. However, there arises a problem that, with a recent trend of increase in the degree of integration of semiconductor devices, monitoring inspection by setting up probes has become more difficult.
Moreover, there arises a problem that, with a recent progress of increase in the pin number of semiconductor devices, the cost of monitoring inspection by setting up probes has become higher.
Herein, the reason why the conventional JTAG boundary scan register 9 shown in FIG. 5 cannot be connected to an analog terminal will be described. Since the built-in JTAG boundary scan register 9 of the semiconductor device 2 is constituted by a digital circuit, when the analog signal of a middle potential is input (for instance, 2.5 V at the digital input terminal of 5 V-interface), there arises a possibility that the increase of power consumption or a breakdown is caused because of the flow of a through current through the transistor in an input stage. Therefore, the JTAG boundary scan register 9 cannot be connected to the analog terminal.